Device Family: Intel® Arria® 10 GT, Intel® Arria® 10 GX, Intel® Arria® 10 SX

Type: Answers

Area: Component, HSIO



Why can’t the Quartus II software automatically merge the Transceiver Avalon Memory-Mapped interfaces of a CDR/CMU PLL and a TX-only channel, of an Arria 10 device?

Description

The Quartus® II software does not support Transceiver Avalon® Memory-Mapped interface auto-merging in Arria® 10 devices. You may encounter fitter errors if your design contains a CDR/CMU PLL and a TX-only channel, which can be merged and placed into one transceiver channel. By default, a CDR/CMU PLL and a TX-only channel are mapped to two different transceiver channels.

Workaround/Fix

To work around this problem, add the following assignment to your Quartus II Settings File (.qsf):

set_instance_assignment -name XCVR_RECONFIG_GROUP MERGE_TX_CDR_PLL -to "TX_Serial_Pin_Name"
set_instance_assignment -name XCVR_RECONFIG_GROUP MERGE_TX_CDR_PLL -to " <CDR/CMU PLL variation name>|altera_xcvr_cdr_pll_a10:xcvr_cdr_pll_a10_0|twentynm_xcvr_avmm:inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst"

set_instance_assignment -name XCVR_RECONFIG_GROUP MERGE_TX_ CDR_PLL -to " <CDR/CMU PLL variation name>|*"