How do I assign a clock in my design to use specific global, regional, dual-regional, or periphery clock networks?

To make an assignment in the Quartus® II software to a specific global, regional, dual-regional, or periphery clock network, apply it to the ~clkctrl version of the signal in your design.

For example, if your design contains a PLL output that should use a global or regional clock network, the following two node names exist after compilation.

<pll name>|altpll_component|mpll_altpll:auto_generated|wire_pll1_clk[0]
<pll name>|altpll_component|mpll_altpll:auto_generated|wire_pll1_clk[0]~clkctrl

The ~clkctrl extension identifies the signal that is fed from the output of a clock control block.

To find these node names, search for the PLL output in either the Node Finder or locate the clock source in the Post-Fit Technology Map Viewer.

Examples of the correct assignments of PLL clock outputs to specific clock resources are shown below:

• For global clock resource:

  set_location_assignment CLKCTRL_G2 -to "<pll name>|altpll:altpll_component|mpll_altpll:auto_generated|wire_pll1_clk[0]~clkctrl"

• For regional clock resource:

  set_location_assignment CLKCTRL_R1 -to "<pll name>;|altpll:altpll_component|mpll_altpll:auto_generated|wire_pll1_clk[0]~clkctrl"

• For dual-regional clock resource, note that two ~clkctrl nodes exist for a dual-regional clock network, one for each regional network:

  <pll name>|altpll:altpll_component|mpll_altpll:auto_generated|wire_pll1_clk[0]~clkctrl
<pll name>|altpll:altpll_component|mpll_altpll:auto_generated|wire_pll1_clk[0]~clkctrl_d

set_location_assignment CLKCTRL_R1 -to "<pll name>|altpll:altpll_component|mpll_altpll:auto_generated|wire_pll1_clk[0]~clkctrl"
set_location_assignment CLKCTRL_R11 -to "<pll name>|altpll:altpll_component|mpll_altpll:auto_generated|wire_pll1_clk[0]~clkctrl_d"

• For periphery clock resource:

  set_location_assignment CLKCTRL_X0_Y74_N127 -to <clock source>~clkctrl