Beginning with the Quartus® II software version 13.0, the memory controllers with UniPHY IP generate an extra port
afi_reset_export_n when PLL sharing is not enabled or PLL sharing is set to master. This port is a duplication of the
afi_reset_n port and can be connected to the PLL sharing slave controllers's
afi_reset_n port. If the PLL is not being shared, the
afi_reset_export_n port can be left floating. The
afi_reset_n output port should still be used to connect to the user logic.
Refer to the example design generated with the UniPHY IP for an example of how this port is used.