Device Family: Arria® II GZ

Device Family: Arria® V GT

Device Family: Arria® V GX

Device Family: Arria® V GZ

Device Family: Arria® V ST

Device Family: Arria® V SX

Device Family: Cyclone® V E

Device Family: Cyclone® V GT

Device Family: Cyclone® V GX

Device Family: Cyclone® V SE

Device Family: Cyclone® V ST

Device Family: Cyclone® V SX

Device Family: Stratix® III

Device Family: Stratix® IV E

Device Family: Stratix® IV GT

Device Family: Stratix® IV GX

Device Family: Stratix® V E

Device Family: Stratix® V GS

Device Family: Stratix® V GT

Device Family: Stratix® V GX

Type: Answers

Area: EMIF

Area: Intellectual Property


IP Product: RLDRAM II Controller with UniPHY

What is the afi_reset_export_n port used for?

Description

Beginning with the Quartus® II software version 13.0, the memory controllers with UniPHY IP generate an extra port afi_reset_export_n when PLL sharing is not enabled or PLL sharing is set to master. This port is a duplication of the afi_reset_n port and can be connected to the PLL sharing slave controllers's afi_reset_n port. If the PLL is not being shared, the afi_reset_export_n port can be left floating. The afi_reset_n output port should still be used to connect to the user logic.

Refer to the example design generated with the UniPHY IP for an example of how this port is used.