Article ID: 000079245 Content Type: Troubleshooting Last Reviewed: 08/15/2023

What is the afi_reset_export_n port used for?

Environment

  • Quartus® II Subscription Edition
  • DDR3 SDRAM Controller with UniPHY Intel® FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    What is the afi_reset_export_n port used for?

     

     

    Resolution

    Beginning with the Quartus® II software version 13.0, the memory controllers with UniPHY IP generate an extra port afi_reset_export_n when PLL sharing is not enabled or PLL sharing is set to master.

    This port is a duplication of the afi_reset_n port and can be connected to the PLL sharing slave controllers' afi_reset_n port. If the PLL is not being shared, the afi_reset_export_n port can be left floating. The afi_reset_n output port should still be used to connect to the user logic.

    Refer to the example design generated with the UniPHY IP for an example of how this port is used.

    Related Products

    This article applies to 20 products

    Cyclone® V SX SoC FPGA
    Stratix® III FPGAs
    Stratix® IV E FPGA
    Stratix® IV GT FPGA
    Stratix® IV GX FPGA
    Stratix® V E FPGA
    Stratix® V GS FPGA
    Cyclone® V GT FPGA
    Arria® V GT FPGA
    Arria® V GZ FPGA
    Cyclone® V E FPGA
    Cyclone® V GX FPGA
    Arria® V ST SoC FPGA
    Arria® V SX SoC FPGA
    Cyclone® V SE SoC FPGA
    Cyclone® V ST SoC FPGA
    Stratix® V GT FPGA
    Stratix® V GX FPGA
    Arria® II GZ FPGA
    Arria® V GX FPGA

    Need more help?

    Contact support

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.