Device Family: Arria® II GZ, Arria® V, Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Cyclone® V, Cyclone® V E, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX

Type: Answers

Area: EMIF, Intellectual Property

IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Why do the CSR registers report ECC data errors when the read data is not corrupted?


The configuration and status registers (CSR) may report bit errors even though the traffic generator monitor does not detect data corruption when you enable both error correction code (ECC) and CSR in the DDR3 hard memory controller (HMC) MegaWizard™ GUI settings. This discrepancy is seen because the memory controller reads data from uninitialized locations.


The workaround of this issue is to load the memory with known content when you enable the ECC feature.