The configuration and status registers (CSR) may report bit errors even though the traffic generator monitor does not detect data corruption when you enable both error correction code (ECC) and CSR in the DDR3 hard memory controller (HMC) MegaWizard GUI settings. This discrepancy is seen because the memory controller reads data from uninitialized locations.
Device Family: Arria® II GZ, Arria® V, Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Cyclone® V, Cyclone® V E, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX
Area: EMIF, Intellectual Property
The workaround of this issue is to load the memory with known content when you enable the ECC feature.