Device Family: Intel® Arria® 10 GT, Intel® Arria® 10 GX, Intel® Arria® 10 SX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Why are some DDR4 signals unconstrained in TimeQuest?

Description

You may see the following signals show up as unconstrained input and output ports in TimeQuest:

mem_alert_n

mem_dbi_n

mem_ck/mem_ck_n

mem_dqs_n

These signals should have false path assignments.

Workaround/Fix

Add the following assignments to the DDR4 SDC file under the FALSE PATH CONSTRAINTS section:

    set_false_path -from [get_ports {*alert_n*}]
    set_false_path -from [get_ports {*dbi_n*}]
    set_false_path -to [get_ports {*dbi_n*}]
    set_false_path -to [get_ports {*mem_ck*}]
    set_false_path -to [get_ports {*mem_ck_n*}]
    set_false_path -to [get_ports {*mem_dqs_n*}]

This issue will be fixed in a future version of the Quartus® II software.