Device Family: Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Cyclone® V E, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Warning (332174): Ignored filter at <variation name>_p0.sdc(679): _UNDEFINED_PIN__driver_core_clk could not be matched with a clock

Description

When you use the hard memory controller in the Quartus® II software version 12.0sp2 and compile the files generated by Qsys or the files in the folder instead of the <variation name>_example_design/example project folder generated by IP Megawizard, you may get the following warning.

Warning (332174): Ignored filter at _p0.sdc(679): _UNDEFINED_PIN__driver_core_clk could not be matched with a clock

pll_driver_core_clk is the driver clock only for the example project. If you are not using the example project, Quartus does not recognize the driver clock in the user logic. This causes the warning to appear.

Workaround/Fix

You can safely ignore the warning and create your own timing constraints for the PLL reference clock.

This problem is fixed in the Quartus II software version 13.0.