Device Family: Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Cyclone® V E, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX

Type: Answers

Area: EMIF, Intellectual Property

IP Product: DDR3 SDRAM Controller Supporting UniPHY

Why do I see incorrect read data when using a Hard Memory Controller with multiple MPFE ports?


When performing write and read transactions to the hard memory controller (HMC) MPFE ports, you may observe that the read transactions are performed before the write transactions even when the write priority is higher. As a result, the read data may be incorrect.

For example, if your HMC MPFE ports are set as follows:

Port0 configured as write-only, priority set to 7 and weight set to 0
Port1 configured as read-only, priority set to 1 and weight set to 0

And you perform a write request on Port0 to address 'addr0' with data 'data0' and a read request on Port1 to address 'addr0' simultaneously, the data read back should always be 'data0'. There is a problem in the HMC where the read data is not as expected.


The workaround is to delay performing read requests to an address range until all write requests to the same address range are completed. An alternative approach is to read from a different region of memory than the one that is being written to.

This will be fixed in a future release of the Quartus® II software.