Device Family: Arria® II GZ

Device Family: Arria® V GT

Device Family: Arria® V GX

Device Family: Arria® V GZ

Device Family: Arria® V ST

Device Family: Arria® V SX

Device Family: Cyclone® V E

Device Family: Cyclone® V GT

Device Family: Cyclone® V GX

Device Family: Cyclone® V SE

Device Family: Cyclone® V ST

Device Family: Cyclone® V SX

Device Family: Stratix® III

Device Family: Stratix® IV E

Device Family: Stratix® IV GT

Device Family: Stratix® IV GX

Device Family: Stratix® V E

Device Family: Stratix® V GS

Device Family: Stratix® V GT

Device Family: Stratix® V GX

Type: Answers

Area: EMIF

Area: Intellectual Property


IP Product: RLDRAM II Controller with UniPHY

WARNING: altera_mem_if_sequencer_cpu_no_ifdef_params_sim_cpu_inst_test_bench/av_ld_data_aligned_unfiltered is x

Description

When simulating UniPHY-based memory controllers, you may experience the above warning. The warning is caused by two uninitialized register files that are inadvertly accessed during the startup of the Nios sequencer in the memory controller.

Workaround/Fix

To fix this warning, implement the following workaround:

1) Open the altera_mem_if_sequencer_cpu_no_ifdef_params_sim_cpu_inst.v file

2) For the two instances of altsyncram, add the following line:

the_altsyncram.intended_device_family = "STRATIXIV"

Change the intended_device_family to the FPGA device family being used (STRATIXIII, STRATIXIV, etc.). The instance should look like the following:

altsyncram the_altsyncram (

.address_a (wraddress),

.address_b (rdaddress),

.clock0 (clock),

.data_a (data),

.q_b (ram_q),

.wren_a (wren) );

defparam

the_altsyncram.address_reg_b = "CLOCK0",

the_altsyncram.intended_device_family = "STRATIXIV",

the_altsyncram.maximum_depth = 0,

the_altsyncram.numwords_a = 32,

the_altsyncram.numwords_b = 32,

the_altsyncram.operation_mode = "DUAL_PORT",

the_altsyncram.outdata_reg_b = "UNREGISTERED",

the_altsyncram.ram_block_type = "AUTO",

the_altsyncram.rdcontrol_reg_b = "CLOCK0",

the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",

the_altsyncramthe_altsyncram.width_b = 32,

the_altsyncram.widthad_a = 5,

the_altsyncram.widthad_b = 5;

This issue will be fixed in a future version of the Quartus® II software.