Device Family: Stratix® III, Stratix® IV E, Stratix® IV GT, Stratix® IV GX, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: Renewal QDRII / II+ Controller with UniPHY

Why is the QDRII+ SRAM UniPHY based controller IP not generating QVLD signal for the interface?

Description

QVLD signal is not generated because it is not used by the QDRII+ SRAM UniPHY based controller IP to determine if the data coming back is valid or not.

QDRII+ SRAM UniPHY based IP uses calibration process to determing the exact read latency i.e. how long does it take for the valid data to come back from the QDRII+ SRAM device after a read command is given by the IP.