Device Family: Arria® II GX, Arria® II GZ, Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Cyclone® IV GX, Cyclone® V GT, Cyclone® V GX, Cyclone® V ST, Cyclone® V SX, Stratix® II GX, Stratix® IV GT, Stratix® IV GX, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: Component, HSIO



Can the transceiver PHY in Gigabit Ethernet mode compensate for clock frequency differences between the recovered clock and the reference clock during 1000BASE-X/SGMII auto-negotiation?

Description

No, the transceiver PHY (ALT2GXB, ALT_GXB and Native PHY IP's) in Gigabit Ethernet mode cannot compensate for clock frequency differences between the recovered clock and the reference clock during 1000BASE-X/SGMII auto-negotiation.

The Rate Match FIFO in the transceiver PHY is capable of inserting or deleting the first two bytes of /C2/ ordered sets during auto-negotiation. However, the insertion or deletion of the first two bytes of /C2/ ordered sets could cause the 1000BASE-X/SGMII PCS state machine to function incorrectly.

Workaround/Fix

Refer to Application Note AN 537 Implementing UNH-IOL Test Suite Compliance in Arria® GX and Stratix® II GX Gigabit Ethernet Designs (PDF).

This application note can be applied to all device families.