Device Family: Stratix® III, Stratix® IV E, Stratix® IV GX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: Renewal RLDRAM II Controller

Why is there a mismatch between the local Avalon interface data width and memory interface data width when generating UniPHY based DDR2 SDRAM, DDR3 SDRAM, QDRII SRAM and RLDRAMII controller IPs?

Description

You will see a mismatch between the local Avalon interface data width and memory interface data width when generating UniPHY based DDR2 SDRAM, DDR3 SDRAM, QDRII SRAM, and RLDRAMII controller if you have turned on the option "Generate power-of-2 bus widths". This option is used when implementing the QDRII IP in SOPC Builder since SOPC Builder does not support bus width other than power of 2. So, if you are not implementing your design in SOPC Builder, you should not turn this option ON. When this option is turned on, the Avalon-MM side data bus width is rounded down to the nearest power of 2.

 

For example, if you are generating a 36 bit Half Rate QDRII SRAM interface with burst of 4, you expect the IP to generate 144 bits wide Avalon-MM side data bus but if you have turned on the option "Generate power-of-2 bus widths", the IP does not generate connections for bits 128 to 143. User data can not be written to these bits and read from these bits. The disregarded local data bits do not correspond to specific data pins that are completely disconnected, but correspond instead to a fraction of the transfers across a larger number of data pins. E.g. with 36 bit Half Rate interface, data on 16 pins (DQ pins 20 to 35) will be ignored 1/4 of the time because of the mapping of the DQ pin to the local interface.

 

DQ0 is mapped to 0, 36, 72, 108 local bits

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DQ34 is mapped to 34, 70, 106, 142 and

DQ35 is mapped to 35, 71, 107, 143

 

Therefore, to ignore bits 128 to 143, data from 16 pins will be ignored 1/4 of the time.