Device Family: Arria® V GX, Cyclone® V, Cyclone® V E, Stratix® V

Type: Answers

Area: Component, EMIF


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Are single bit errors corrected when the <strong>Enable Error Detection and Correction Logic</strong> option is selected and the <strong>Enable Auto Error Correction</strong> option is disabled in the DDR3 SDRAM controller with UniPHY?

Description

When using the DDR3 controller with UniPHY, the Enable Error Detection and Correction Logic option is enabled, any data coming back from memory via read command with single bit errors will be corrected automatically regardless of whether the auto correction feature is enabled or not. This is done by the decoder which performs single bit error corrections.

The Enable Auto Error Correction option is an extra feature to enable another read-modify-write process to correct the single bit error in the memory device. The Enable Error Detection and Correction Logic option can only correct the read data, not the wrtten data at the memory device.