Device Family: Intel® Arria® 10 GT

Device Family: Intel® Arria® 10 GX

Device Family: Intel® Arria® 10 SX

Device Family: Arria® V GT

Device Family: Arria® V GX

Device Family: Arria® V GZ

Device Family: Arria® V ST

Device Family: Arria® V SX

Device Family: Cyclone® V E

Device Family: Cyclone® V GT

Device Family: Cyclone® V GX

Device Family: Cyclone® V SE

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Device Family: Stratix® IV E

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Device Family: Stratix® V GT

Type: Answers

Area: Intellectual Property


IP Product: DSP Builder

Why do I see invalid read data when DSP Builder memory interace bus has an NCO or FIR attached to it?

Description

You may see invalid read data at the end of a memory read burst or at the end of any single memory read if you have an NCO or FIR component on your DSP Builder memory interface bus.

Workaround/Fix

This is due to a problem in the Quartus® II software.

The workaround is to move the NCO or FIR filter to a non-zero address.

This is scheduled to be fixed in a future release of the Quartus II software.