Due to a bug in the Quartus® II software, a design which has an Altera® LVDS SERDES IP core configured in TX mode and an Altera LVDS SERDES IP core configured in RX Soft-CDR mode assigned to the same IO bank in an Arria® 10 device will fail at the fitter stage. This is because the PLL instances within the two IP cores will not be correctly merged by the Quartus II software and so different PLLs will be required for the different Altera LVDS SERDES IP cores. Each I/O bank has only one I/O PLL though.
This problem only affects the RX Soft-CDR configuration. RX Non-DPA or RX DPA-FIFO configurations are not affected.
Note that the Triple Speed Ethernet IP core uses Altera LVDS SERDES IP configured in RX Soft-CDR mode.