Device Family: Stratix® IV GX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

What are controller-scheduled autocorrections?

Description

In the DDR3 UniPHY version 11.0 memory controller, the controller scheduled autocorrections are read/write transactions that take place after a single bit error is detected and autocorrection is enabled. The controller must write back the corrected data to memory.

The controller performs a read-modify-write (RMW) transaction during an autocorrection. The reason a RMW is performed instead of a write is because there might be another write to the same location before autocorrection occurs. The controller needs to make sure it is correcting the latest data in the memory.