Device Family: Arria® V ST, Arria® V SX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: Renewal DDR3 SDRAM Controller MegaCore supporting UniPHY

Does the Advanced clock phase control adjustment in the HPS DDR3 work?

Description

You may notice the Advanced clock phase control setting in the HPS GUI PHY Settings tab. Changing the phase value has no effect on the phase of the PLL output clocks.

Workaround/Fix

The Advanced clock phase control adjustment will be removed in a future version of the Quartus® II software.