Device Family: Arria® V ST, Arria® V SX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX
Area: EMIF, Intellectual Property
IP Product: Renewal DDR3 SDRAM Controller MegaCore supporting UniPHY
You may notice the Advanced clock phase control setting in the HPS GUI PHY Settings tab. Changing the phase value has no effect on the phase of the PLL output clocks.
The Advanced clock phase control adjustment will be removed in a future version of the Quartus® II software.