Description
When running the DDRx with UniPHY version 11.0 controller in certain situations, you may notice inefficiencies on the memory bus that were not present when running the DDRx with UniPHY 10.1 controller. These inefficiencies lead to gaps between read or write bursts and decrease the throughput of the bus.
The inefficiencies are due to the controller requiring an extra clock cycle between back-to-back activates (to different banks). A delay in activate will cause a delay in the subsequent read/write transaction resulting in the de-assertion of local_ready. This results in the controller being less efficient than the 10.1 version.
This issue will be fixed in a future version of the Quartus® II software.
Resolution
The workaround is to open the alt_mem_ddrx_rank_timer.v file and set the local parameter "ENABLE_BETTER_TRRD_EFFICIENCY" to 1.