Device Family: Stratix® IV GX

Type: Answers

Area: Intellectual Property



Why is TSE core unstable on hardware for LVDS variant due to a bug in the generated SDC file?

Description

The existing SDC constraints in TSE generated SDC file which causes TSE core unstable on hardware for LVDS variant:

set clocks_list [get_clocks *]

   foreach_in_collection clock {
    set name [get_clock_info -name ]
      if {[ expr [regexp "altera_tse" ] == 1]} {
          set_clock_groups -exclusive -group [get_clocks ]
         }
    }

 

Solution : Comment out line 410 to 417 of the timing constraint file (SDC) and replace with

set_clock_groups -asynchronous \

-group {altera_tse_mac_rx_clk_0} \

-group {altera_tse_mac_tx_clk_0} \

-group {altera_tse_rx_afull_clk} \

-group {altera_tse_sys_clk} \

-group {altera_tse_ref_clk \

altera_tse_multi_mac_pcs_pma_inst|the_altera_tse_pma_lvds_rx_0|altlvds_rx_component|auto_generated|rx[0]|clk0 \

altera_tse_multi_mac_pcs_pma_inst|the_altera_tse_pma_lvds_rx_0|altlvds_rx_component|auto_generated|pll|clk[0]}

This issue will be fixed in future release.