Why do I receive incorrect data returned from my read TLP requests on my Avalon-Memory Mapped 128 bit Altera Hard IP for PCI Express?

Device Family: Intel® Arria® 10 GT, Intel® Arria® 10 GX, Intel® Arria® 10 SX, Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Cyclone® V GT, Cyclone® V GX, Cyclone® V ST, Cyclone® V SX, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: Intellectual Property

Description

Due to a problem with the Intel® Quartus® II and Prime software versions 15.0, 16.0, 16.1, 17.0 and 17.1 you may see incorrect read data when the PCI* Express link is highly utilized and there are a lot of out-of-order completions. This problem only occurs for PCI* Express Hard IP Avalon®-Memory Mapped 128 bit variants.

When this happens, parts of data from incoming reads may appear in the middle of data from a previous read.

Workaround/Fix

This problem is caused by the memory holding the completion buffer being sized too small.

To workaround this issue follow these steps:

Look in the generated file directories for the file altpciexpav128_rx.v.
Find the line localparam CB_RX_CPL_BUFFER_DEPTH =256;
Change the line to localparam CB_RX_CPL_BUFFER_DEPTH =512;
Find the lines wire[7:0] cplram_wraddr; and wire [7:0] cplram_rdaddr;
Change the wire width from 8-bit to 9-bit:
1. wire [8:0] cplram_wraddr;
2. wire [8:0] cplram_rdaddr;

Version Found: 15.0 and 16.0 to 17.1.1
Version Fixed: 15.1 and 18.0
This issue has been fixed starting in software version 18.0.