Device Family: Intel® Arria® 10 GT, Intel® Arria® 10 GX, Intel® Arria® 10 SX, Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: Intellectual Property


IP Product: PCI Express 1/2/4/8 Lanes (x8)

Why does my Hard IP for PCI Express fail when I have a BAR address size smaller than 4 bits?

Description

Due to a problem with the Quartus® II Software, you can generate invalid BAR sizes smaller than the required 16 bytes specified by the PCI® Local Bus Specification. Qsys will not display any warning messages. The design will not work due to the undersized BARs failing to be enumerated.

Workaround/Fix

To work around this issue, ensure that the connected componets in Qsys result in a BAR size between 16Bytes and 2GBytes (a minimum of 4 address bits).

This is not scheduled to be fixed in a future Quartus II software release.