Device Family: Arria® V GT, Arria® V GX, Arria® V ST, Arria® V SX, Cyclone® V E, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX, Stratix® III, Stratix® IV E, Stratix® IV GT, Stratix® IV GX, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Why does the Avalon interface of my DDR3 UniPHY-based memory controller use Avalon-MM signals instead of Avalon-ST signals?

Description

Due to a problem in the Quartus® II software version 11.1 and later, the DDR3 UniPHY-based memory controllers with the efficiency monitor enabled incorrectly use the Avalon®-MM signal names (e.g. avl_waitrequest) instead of Avalon-ST signal names (e.g. avl_ready). There is a problem during the generate stage of the controller where the Avalon-MM interface of the efficiency monitor is exported instead of the Avalon-ST interface of the controller.

Workaround/Fix

This issue is fixed in the Quartus II software version 12.1 and later.