Device Family: Stratix® IV E, Stratix® IV GT, Stratix® IV GX, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

What is the minimum pulse width timing specification of the global reset signal in UniPHY IP?

Description

Global reset in UniPHY IP is connected to the PLL areset port. Therefore the minimum pulse width of the PLL areset port will be the minimum pulse width specification of the PLL areset port.

You can refer to the PLL specification part of the device datasheet.

For example Minimum pulse width on the PLL areset port is 10ns for Stratix® IV device and Stratix® V device.