Device Family: Stratix® V E

Device Family: Stratix® V GS

Device Family: Stratix® V GT

Device Family: Stratix® V GX

Type: Answers

Area: EMIF

Area: Intellectual Property

IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Error: Could not place PHY_CLKBUF {instance_name}:{instance_name}_inst|{instance_name}_0002: {instance_name}_inst|{instance_name}_p0:p0|{instance_name}_p0_controller_phy:controller_phy_inst|{instance_name}_p0_memphy_top:memphy_top_inst|uphy_clkbuf_memphy Error: PHY_CLKBUF location is occupied


This error will occur if you have multiple master (master for sharing PLL/DLL) external memory interface controller cores being fed by only one clock input pin in Stratix V devices.  Each master interface has to be driven by its own separate PLL, because each PLL can only drive one PHY clock tree. If you try to feed all the interfaces’ PLLs through one clock input, the Fitter will try to use one PLL only and give the error specified above.


To avoid this error, make sure you give a separate input clock to each master interface so the fitter uses separate PLL for each master interface and not try to use just one PLL for all the master controllers.