Device Family: Stratix® V, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: Component



Stratix® V Device Handbook: Known Issues

Description

Issue 338064: Volume 1, Chapter 9 SEU Mitigation for Stratix® V Devices, Version 2015.06.12

In page 9-9, Timing section states as follows:

The CRC_ERROR pin is always driven low during CRC calculation for a minimum of 32 clock cycles. When an error occurs, the pin is driven high once the EMR is updated or 32 clock cycles have lapsed, whichever comes last. Therefore, you can start retrieving the contents of the EMR at the rising edge of the CRC_ERROR pin. The pin stays high until the current frame is read and then driven low again for a minimum of 32 clock cycles.

But this is incorrect. It should state as follows:

The CRC_ERROR pin is always driven low during CRC calculation. When an error occurs, the EDCRC hard block takes 32 clock cycles to update the EMR, the pin is driven high once the EMR is updated. Therefore, you can start retrieving the contents of the EMR at the rising edge of the CRC_ERROR pin. The pin stays high until the current frame is read and then driven low again for 32 clock cycles.

Figure 9-6 states CRC Calculation (minimum 32 clock cycles), but it should state CRC Calculation (32 clock cycles).

Issue 156378: Clock Networks and PLLs in Stratix V Devices, Version 2013.05.06

There are two bullets for requirements when using automatic clock switchover, the first one is incorrect. It says:

"Both clock inputs must be running."

The purpose of automatic clock switchover is to switch between clocks if one stops running. The actual requirement is both clocks need to be running when the FPGA is configured. The bullet should say:

"Both clock inputs must be running when the FPGA is configured."

Issue 123964: Volume 1, Chapter 6: High-Speed Differential I/O Interfaces and DPA in Stratix V Devices, Version 2013.05.06

Figure 6-4 Phase Relationship for External PLL Interface Signals: The phase shift on outclk2 is not correct, the rising edge should occur aligned to the outclk0 rising edge when outclk1 is high.

Issue 111987: Volume 1, Chapter 8: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices, Version 2013.03.04

Table 8-1: Configuration Modes and Features of Stratix V Devices incorrectly states that Partial Reconfiguration is not supported in CvP mode.

CvP mode does support Partial Reconfiguration and this table will be updated in a future revision.

Issue 81980: Volume 1, Chapter 5: I/O Features in Stratix V Devices, Version 1.5

Table 5-1 incorrectly shows that 3.3-V LVCMOS/LVTTL standards are only supported by Stratix V GX and GS devices.  These I/O standards are actually supported by all Stratix V devices.

Issue 86484:  I/O Features in Stratix V Devices, version 1.5.

Programmable Current Strength Table 5-6 is missing the note of:

The default setting in the Quartus II software is 50-ohm OCT RS without calibration for all non-voltage reference and HSTL and SSTL Class I I/O standards. The default setting is 25-ohmOCT RS without calibration for HSTL and SSTLClass II I/O standards.

Issue 79663: Volume 2, Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices, Version 1.7.

Notes to Figure 9-9 is missing information similiar to Note 4 for Notes for Figure 9-8. A new Note will be added to Notes to Figure 9-9 to state "For the appropriate MSEL settings based on POR delay settings, set the slave device MSEL setting to the PS scheme. Refer to Table 9–4 on page 9–7."

Issue 58047: Volume 2, Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices, Version 1.6.

Table 9-14 for the Active Serial (AS) configuration pins (DCLK, AS_DATA0/ASDO, AS_DATA[3..1]) it is stated that "After AS configuration completes, this pin is tri-stated with a weak pull-up resistor." but this is not the case. The AS pins will not be tri-stated when the device enters user mode.

Issue 44730:  I/O Features in Stratix V Devices, version 1.4

OCT for 1.5V LVCMOS outputs is not mentioned in the chapter, but it is supported.  You can make the assignment in the Quartus II software without error.

Issue 39437: Volume 2, Chapter 11: JTAG Boundary-Scan Testing in Stratix V Devices, Version 1.4

Table 11-1 shows the 32-bit IDCODE information for Stratix V devices. 

The correct JTAG ID code for Stratix V A7 devices is

0000 0010 1001 0000 0011 0000 1011 1011 (0x029030DD)

This is incorrectly shown as

0000 0010 1001 0000 0011 0001 1011 1011 (0x029031DD)

Issue 41368: Volume 2, Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices, Version 1.6

In the Notes to Figure 9-11 there is Note 1 that can be a bit misleading. It states "Connect the pull-up resistors to VCCPGM and VCCPD at a 3.0-V supply." This is in fact partially true since VCCPGM can equal to VCCPD but this is not a requirement, VCCPGM and VCCPD can differ in voltages depending on your board requirements. 

For VCCPGM they are required to power all dedicated configuration pins and dual-purpose pins. The supported configuration voltages are 1.8, 2.5, and 3.0 V so that the configuration input buffers do not have to share power lines with the regular I/O buffer in Stratix V devices.

For VCCPD, they must be greater than or equal to VCCIO. If VCCIO is set to 3.0 V, VCCPD must be powered up to 3.0 V. If the VCCIO of the bank is set to 2.5 V or lower, VCCPD must be powered up to 2.5 V. This applies for all the banks containing the VCCPD and VCCIO pins.

Workaround/Fix

Resolved Issues:

Issue 79545:  Stratix V Device Datasheet, Version 2.5

The absolute maximum rating for the following power supplies were updated in version 2.5:

VCCPGM, VCCBAT, VCCPD, VCC, VCCD_PLL, VCCA_PLL

Issue 35432: Volume 1, Chapter 2, DC and Switching Characteristics for Stratix V Devices, Version 2.3

Clarification added to specify differential inputs are powered by VCCPD requiring 2.5V.

Issue 32224: Volume 1, Chapter 2, DC and Switching Characteristics for Stratix V Devices, Version 2.3

VCCBAT supply voltage range updated to include 1.2V to 3.0V.

Issue 390061: Clock Netwoks and PLLs in Stratix V Devices, Version 1.3

PLL locations for 5SGXB5 and 5SGXB6 devices corrected to show which PLLs are driven by CLK0, CLK1, CLK22, CLK23 and CLK8, CLK9, CLK14, CLK15.

Issue 391999: Logic Array Blocks and Adaptive Logic Modules In Stratix V Devices, Version 1.3

Stratix V devices do not support the Register Chain path as shown in version 1.3.

Issue 31778: Volume-3, Chapter-5, Reverse Serial Loopback, Version 2.2

 

Inaccurate statements exist regarding Reverse Serial Loopback being available as a subprotocol under custom configuration.

 

Issue 359605:  Volume 2, Chapter 5, I/O Features in Stratix V Devices, Version 1.3

Note 5 in Table 5–2 incorrectly states that differential clock input buffers are powered by VCC_CLKIN instead of VCCPD.

Issue 380129: Volume 9, Chapter 9, Configuration, Design Security, and Remote System Upgrades in Stratix V Devices, Version 1.3

Figure 9-21 incorrectly shows TDI as tied to pin 7 of the JTAG header instead of pin 9.

Issue 377855: Volume 2, Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices, Version 1.3.

Timing violation will occur in multi-device AS configuration where the slave device is configured by PS mode. Two new restrictions are added to multi-device AS configuration to avoid the timing violation.

Issue 369375: Volume 1, Chapter 8, Hot Socketing and Power-On Reset in Stratix V Devices, Version 1.1

References to the PORSEL pin removed, this pin does not exist in Stratix V devices.

Issue 10006534: Volume 2, Chapter 4, Transceiver Protocol Configurations in Stratix® V Devices, Version 1.0

References of the 10GBaseR protocol were removed.