Device Family: Arria® II GX, Arria® II GZ, Stratix® III, Stratix® IV, Stratix® IV E, Stratix® IV GT, Stratix® IV GX, Stratix® V, Stratix® V E, Stratix® V GT, Stratix® V GX

Type: Answers, Errata

Area: EMIF, Intellectual Property

IP Product: RLDRAM II Memory Controller

Are there any issues with the UniPHY IP Global Signal assignments seen in the Quartus II software Assignments editor after running the <variation_name>_pin_assignments.tcl script?


These assignments which are applied to UniPHY based IP's reset and clock signals are correct and no changes are required by the user.

The assignments are shown with Status “?”. This is due to a display issue in Assignments editor and is planned to be fixed in a future version of the Quartus® II software.