Type: Answers

Area: EMIF, Intellectual Property


IP Product: RLDRAM II Controller with UniPHY

Critical Warning: DDR Timing requirements not met

Description

When an external memory interface with UniPHY is implemented with manual board skew delays, the following warnings in the TimeQuest Timing Analyzer tool may appear. 

Critical Warning: DDR Timing requirements not met
Warning: Write Leveling tDQSS (Slow 900mV 0C Model)
Warning: Write Leveling tDSS/tDSH (Slow 900mV 0C Model)

The tDQSS, tDSS and tDSH timing parameters are associated with write leveling, which is a JEDEC requirement for the memory device (relationship between DQS and CK at each device). This path is external to the FPGA and cannot be fully analyzed by the TimeQuest Timing Analyzer tool. The analysis is done via calculations in the report_ddr script based on the board skew delays.

Workaround/Fix

To work around this issue, please double check all the board skew settings in the MegaWizard or Qsys GUI to make sure all the parameters comply with the Altera recommended layout guidelines.