Device Family: Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Error: Output port OUTCLK of stratixv_phy_clkbuf atom "Hierarchy|{instance_name}_p0_memphy_top:memphy_top_inst|uphy_clkbuf_memphy" has one or more illegal fan-outs.

Description

You may get this error along with the following error when compiling DDR3 SDRAM UniPHY based controller generated for Stratix® V device in Quartus® II software version 11.0 or earlier in Quartus II software version 11.0SP1.

Error: The stratixv_clkena Atom "Hierarchy|{instance_name}_p0_memphy_top:memphy_top_inst|pll_write_clk~CLKENA0" is an illegal destination

This error occurs due to the following global signal assignment made in QSF file for pll_write_clk signal

set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to "Hierarchy|{instance_name}|pll_write_clk"

This assignment is made by the version of the IP before 11.0SP1 and is present in the QSF when you move to Quartus II version 11.0SP1 which puts this clock on PHY clock tree instead of global clock tree that was used in the version before it.

Workaround/Fix

To fix this issue, comment out any global signal assignments made to pll_write_clk signal in your QSF file or run the {instance_name}_pin_assignments.tcl file in Quartus II software version 11.0SP1 after regenerating the core.