This is due to the reason that reset sequencer will restart the transceiver's reset sequence and bring the TSE PCS into reset state when TSE PCS detects a link down. The TSE PCS will be out only from reset state when the transceiver reset sequence is complete and TSE PCS detects link up condition.
The following workaround provides the solution to ensure PCS block will not go in to reset state when the transceiver reset sequence is started or link down is detected.
1. Browse to project's triple_speed_ethernet-library folder and open the clear-text RTL file 'altera_tse_pcs_pma_gige.v '.
2. At line 247, modify the following code:
assign PCS_reset = reset | rx_digitalreset_sqcnr_clk;
assign PCS_reset = reset;
By removing rx_digitalreset_sqcnr_clk signal, it ensures TSE PCS soft logic is not depending on the transceiver's reset sequencer. However, it will still be able to go to reset mode if reset input is asserted.
After the modification, please recompile Triple Speed Ethernet project.