Device Family: Arria® V, Arria® V GX

Type: Answers

Area: EMIF, Intellectual Property

IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Why my DDR3 HMC example designs targeting Arria V devices with C5 speed grade at 533MHz failed timing?


The reason for the timing issue is large clock uncertainty. To minimize the clock uncertainty from the PLL, you need to try to maximize the VCO frequency and also keeping the M counter value as small as possible.  The exact values will depend on the design and the frequencies that are acceptable in the system.


Change the frequency of pll reference clock to get lower clock uncertainty to resolve the timing failure.


For example, DDR3 HMC example designs use 125MHz as the reference clock. You may get setup/removal timing failures related to pll_avl_phy_clk. M / N Counters ratio is 145/17 and clock uncertainty from pll_afi_clk to pll_avl_phy_clk is 0.27ns.

When you change the reference clock frequency to 100MHz, M / N Counters ratio would be 16/3 and clock uncertainty would be 0.08ns. This can solve the timing violation.