Device Family: Arria® V GT, Arria® V GX, Arria® V ST, Arria® V SX, Cyclone® V E, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: Renewal DDR3 SDRAM Controller MegaCore supporting UniPHY

When using the UniPHY-based hard memory controller, why do I see timing violations between the ports on the MPFE block?

Description

You may see timing violations between the ports on the MPFE block using different clock frequencies, because these timing paths are not automatically cut by the Quartus II software.

Workaround/Fix

There are no paths between the MPFE ports in the UniPHY-based hard memory controller. The failing paths can be safely cut using either the set_clock_groups or set_false_path SDC commands. Refer to the Quartus II TimeQuest Timing Analyzer (.PDF) document for more information on the SDC commands.