Device Family: Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Cyclone® V E, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX, Stratix® III, Stratix® IV E, Stratix® IV GT, Stratix® IV GX, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Why is my HPS DDR3 controller failing calibration?

Description

Your HPS DDR3 controller generated with Quartus® II software version 13.0 or 13.0sp1 may experience a calibration failure and produce the following debug messages in the debug output text file:

test_load_patterns(0,ALL) => (85 == 255) => 0

Guaranteed read test failed

SEQ.C: Calibration Failed

SEQ.C: Error Stage : 1

SEQ.C: Error Substage: 1

SEQ.C: Error Group : 0

There is a known issue where the HPS Vref pins draw high current causing the Vref voltage to drop and DDR3 calibration to fail.

Workaround/Fix

Install the Quartus II 13.0SP1 release DP5 patch. See the link in Related Solutions below.

The same fix is also available as a separate patch (1.34) for the Quartus II 13.0SP1 release. It is recommended that users install the DP5 patch, but should a separate patch for only the HPS Vref issue be required, please contact Altera.

This issue will be fixed in a future version of the Quartus II software.