Device Family: Stratix® V, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property

IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

When using UniPHY IP in Stratix V devices, what are the options for changing the calibrated OCT termination values from the default values ?


The default Input and Output calibrated termination resistance values are applied by running the <IP_name>_p0_pin_assignments.tcl script.
After performing board level simulations and optimising signal integrity, users may want to consider changing these values.


Listed below are the main rules for calibrated OCT :

1) Ensure that the calibrated termination resistance values are supported for the signal I/O standard being used and the RZQ resistance value to be fitted.
Refer to the OCT section of  the I/O chapter of the device handbook for further details.

2) 6 pins within an IO block must all have the same calibrated termination resistance values as described in this solution :

How do DQ grouping pin assignments affect On-Chip Termination (OCT) block usage in Stratix V devices?

3) A single OCT calibration block (Termination Control Block) can support I/O pins with calibrated termination requirements of one series and one parallel resistance value.
These series and parallel calibrated termination resistances can be different values.

For example, with an RZQ pin with a 240 ohms resistor fitted to GND and a DDR3L interface using SSTL-135 I/O, a series calibrated termination of 34 ohms and a parallel calibrated termination of 40 ohms is supported.

After making any changes to the UniPHY IP calibrated OCT resistance values of the input and output termination assignments, verify the project fits successfully and closes timing. Check for any OCT associated warnings or critical warnings.