Device Family: Arria® II GZ, Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX, Stratix® III, Stratix® IV E, Stratix® IV GT, Stratix® IV GX, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

How do I reduce the UniPHY DDR3 controller pulsing avl_ready low on the Avalon interface?

Description

Depending on the type of accesses on the controller's Avalon® interface, you may see the avl_ready pulse low in some situations where it should not be expected. This occurs because of the way the Avalon interface works.

Workaround/Fix

Listed below are some suggestions which may improve the efficiency of the Avalon interface by minimizing avl_ready pulsing low during burst accesses.
  1. Increase the value of the MegaWizard™ parameter Command Queue Lookahead Depth. The controller uses an open page policy where it tries to keep banks open to avoid unnecessary precharge and activate cycles. Typically, it requires a Command Queue Lookahead Depth value of the number of pages to keep open simultaneously and at least 2 more for new commands entering the controller. Note that increasing this parameter will use more FPGA logic resources, and timing closure may be more challenging.
  2. Set the MegaWizard parameter Memory Parameters -> Mode Register 1 -> Memory additive CAS latency option to Disabled.
  3. In the DDR3 UniPHY controller\'s top level variation file, find the parameters MAX_PENDING_WR_CMD and MAX_PENDING_RD_CMD. Change these values to 32 and regenerate the DDR3 controller.
  4. If using a half rate controller and Avalon burst accesses of size 1, to improve the efficiency of the controller, enable the burst merge option.

For more information on the Avalon interface, refer to the Avalon Interface Specifications.