Device Family: Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: Component, EMIF

IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Why does my DDR3 Uniphy *|pll_c2p_write_clk clock disappear from my TimeQuest reports during certain compilations?


For certain configurations of the DDR3 UniPHY-based memory controller, the *|pll_c2p_write_clk clock may not be listed in the clocks report during timing analysis. This omission may occur when two of the memory controller PLL counter outputs have the same settings and are merged together. In this case, the *|pll_c2p_write_clk clock will be merged into the *|pll_afi_clk which is why it is no longer visible in the TimeQuest reports.


No workaround is necessary because the PLL counter merging is valid and all timing paths that were originally associated with the *|pll_c2p_write_clk clock is now associated with *|pll_afi_clk clock.