Article ID: 000079111 Content Type: Product Information & Documentation Last Reviewed: 08/13/2012

How can I stop the Quartus II software from merging PLLs in my design?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT

Description

You can disable PLL merging in the Quartus® II software by adding the following assignment to your .qsf file:

set_global_assignment -name AUTO_MERGE_PLLS OFF

This setting can be also be accessed from the Assignments Menu, by clicking on Settings -> Fitter Settings -> More Fitter Settings.

Stratix® V FPGAs

Stratix® IV FPGAs

Stratix® III FPGAs

Stratix® II FPGAs

Stratix® FPGAs

Intel® MAX® 10 FPGAs

Cyclone® V FPGAs and SoC FPGAs

Cyclone® IV FPGAs

Cyclone® III FPGAs

Cyclone® II FPGA

Cyclone® FPGAs

Intel® Arria® 10 FPGAs and SoC FPGAs

Arria® V FPGAs and SoC FPGAs

Arria® II FPGAs

Arria® GX FPGA

¹

All postings and use of the content on this site are subject to Intel.com Terms of Use.