Device Family: Intel® Arria® 10 GT, Intel® Arria® 10 SX, Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: Intellectual Property


IP Product: PCI Express 1/2/4/8 Lanes (x8)

BARs must be disabled when using Root Port

Description

You will see this message if you have enabled Base Address Registers (BARs) for the Avalon Memory-Mapped (Avalon-MM) of the Altera® Hard IP core for PCI Express® with Port type set to Native Endpoint, but then switch to Port type Root Port.

For example:

1)  Enable BAR0 (32-bit non prefetchable)
2)  Enable BAR1 (32-bit non prefetchable)
3)  Change the Port Type from Native endpoint to Root port

Workaround/Fix

To work around this issue:

Re-select the Endpoint type, disable all BARs, then re-select Root Port type.

This behavior is not scheduled to be changed in a future Quartus® II software version.