Article ID: 000084734 Content Type: Troubleshooting Last Reviewed: 07/13/2023

Are there any known issues with the transceiver Tx signal integrity that may increase the BER on Stratix® V GX production silicon devices?

Environment

  • Quartus® II Subscription Edition
  • PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Yes, due to a bug in Quartus® II software versions 12.0, 12.0SP1, and 12.0SP2, you may see a periodic glitch on the transceiver Tx pins of Stratix® V GX production devices.

    The glitch will produce a marginal increase in Tx jitter which may result in a marginally higher Bit Error Rate (BER).

     

     

    Resolution

    To fix this problem, install the appropriate patch below.

    Patches for Quartus® II software version 12.0 dp2

    Patches for Quartus® II software version 12.0 dp3

    Patches for Quartus® II software version 12.0 SP1

    Patches for Quartus® II software version 12.0 SP2

    After installing the patch, regenerate your transceiver PHY and/or QSYS system and recompile your project.

     

    Related Products

    This article applies to 2 products

    Stratix® V GX FPGA
    Stratix® V FPGAs