Device Family: Arria® V ST

Intel Software: Quartus II

Type: Answers

Area: EMIF

Last Modified: September 12, 2013
Version Found: v13.0 Service Pack 1
Version Fixed: v13.1
IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY
Bug ID: N/A

Error (175001): Could not place HPHY


When you implement a DDR3L Hard Memory Controller (HMC) and DDR3L Hard Processor System (HPS) in one project using Arria® V ST device in Quartus® II software version 13.0SP1, you may see the following error messages during the compilation fitter stage.

Error (175001): Could not place HPHY
Error (175006): Could not find path between the HPHY and destination pin

The error message indicates that you can't place the HMC to a legal location. But when you compile DDR3L HMC or  DDR3L HPS independently, the fitter is successful which indicates the pin locations for HMC and HPS are correct.

The error message doesn't point out the root cause for this issue. You may see the following further fitter error when you add dedicated pin location assignments to all interface signals for DDR3L HMC and DDR3L HPS.

Error (175020): Illegal constraint of pin to the region (xx, xx) to (xx, xx): no valid locations in region

Error (175005): Could not find a location with: OCT_CAL_BLOCK_ID of 1 (1 location affected)

There should be no interaction between HMC OCT and HPS OCT.


To resolve this issue, add a "TERMINATION_CONTROL_BLOCK " assignment to the mem_reset_n signal of DDR3L HMC  in the .QSF  file and then fitter should be successful.

set_instance_assignment -name TERMINATION_CONTROL_BLOCK "<DDR3L HMC variation>|altera_mem_if_oct_arriav:oct0|sd1a_0" -to mem_reset_n