Article ID: 000073756 Content Type: Troubleshooting Last Reviewed: 08/14/2023

Why does the example design simulation fail when the UniPHY controller is generated with PHY only option?

Environment

  • Quartus® II Software
  • DDR3 SDRAM Controller with UniPHY Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    When simulating the example design of a UniPHY controller with PHY only option, some ports in the controller *_e0_c0 instance are not connected, causing the simulation to fail.

     

     

    Resolution

    The workaround is to tie all unconnected input ports to zero in the *_example_sim_e0_c0 instance of the *_e0.v file.

    This issue has been fixed in the Quartus® II software 13.1 version.

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