Description
When simulating the example design of a UniPHY controller with PHY only option, some ports in the controller *_e0_c0 instance are not connected, causing the simulation to fail.
Resolution
The workaround is to tie all unconnected input ports to zero in the *_example_sim_e0_c0 instance of the *_e0.v file.
This issue has been fixed in the Quartus® II software 13.1 version.