Device Family: Arria® II GZ, Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Cyclone® V E, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX, Stratix® III, Stratix® IV E, Stratix® IV GT, Stratix® IV GX, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property

IP Product: UniPHY Controller

Why does the example design simulation fail when the UniPHY controller is generated with PHY only option?


When simulating the example design of a UniPHY controller with PHY only option, some ports in the controller *_e0_c0 instance are not connected causing the simulation to fail.


The workaround is to tie all unconnected input ports to zero in the *_example_sim_e0_c0 instance of the *_e0.v file.

This issue will be fixed in a future release of the Quartus® II software.