Yes, there is an issue with DOFF_N pin behaviour, this signal is asserted high all the time in the Quartus® II software 10.0SP1 and earlier versions. While this may work for Cypress QDRII SRAM and other memory devices, it may not work for Gigasemi QDR II SRAM memory devices as they have different initialization sequence.
To workaround the issue if you are using Gigasemi QDR II SRAM device please change the RTL to hold DOFF_N signal low during startup and immediately after reset, and then when the sequencer gets to the STATE_STABLE state, at which point the PLL on the FPGA is locked and the output clock is stable drive DOFF_N high and wait at least 2048 cycles for the DLL on the memory device to lock.
This issue will be fixed in future version of the Quartus II software.