Device Family: Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property

IP Product: FPGA Development Kit, Stratix V Edition

Can I use Report DDR for ALTDQ_DQS2 megafunction?


In the Quartus® II software, the Report DDR panel does not support ALTDQ_DQS2 megafunction. The Report DDR panel is a static timing analysis macro specific to Altera® memory interface IP. It calls the <core name>_report_timing.tcl script in the back-end.

The ALTDQ_DQS2 and ALTDDIO megafunctions do not have this macro and don't come with a script. Users are expected to write their own timing constraints in the form of synopsys design constraint (.sdc) files. Timing analysis is performed the same as for any other design.