Device Family: Intel® Arria® 10 GT, Intel® Arria® 10 GX, Intel® Arria® 10 SX
Type: Answers
Area: Tools


Last Modified: November 03, 2014
Version Found: v14.0 Arria 10 Edition

Why do I see timing constraint problems with the <CODE>tx_clkout</CODE> and <CODE>pipe_hclk</CODE> output clocks in Arria 10 PIPE designs?

Description

The tx_clkout and pipe_hclk output clocks are incorrectly constrained in the PIPE designs in the Quartus® II Software version 14.0 Arria® 10 Edition.

Workaround/Fix

To fix this problem, in your top level Synopsys Design Constraints (.SDC) file, follow these steps:

  1. Include the derive_pll_clock constraint in your SDC file.
  2. In a line beneath the derive_pll_clock constraint, use the remove_clock constraint to remove tx_clkout and pipe_hclk.
  3. Recreate these clocks at their interfaces using the create_clock SDC command

This is scheduled to be fixed in a future version of the Quartus II software. 

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