Device Family: Arria® V GX, Cyclone® V GX

Type: Answers

Area: EMIF, Intellectual Property

IP Product: DDR3 SDRAM Controller Supporting UniPHY

Error (332000): can't read "local_pll_driver_core_clk": no such variable


When you use LPDDR2 SDRAM Hard Memory Controller in Quartus® II software version 13.0SP1, you will see the following fitter errors when you compile your project.

Error (332000): can't read "local_pll_driver_core_clk": no such variable
    while executing
"set_min_delay -from -to 0.500"
    ("foreach" body line 504)
    invoked from within
"foreach { inst } {
    if { [ info exists pins ] } {
        # Clean-up stale content
        unset pins
    array set pins $<variation name>_p0_ddr_db()
(file "<variation name>/<variation name>_p0.sdc" line 159)

The reason for this issue is that <variation name>_p0.sdc doesn’t create “local_pll_driver_core_clk” since it doesn’t know the clock for the driver and MPFE ports in customer’s user logic.

But the error will not appear if you compile the example project generated by IP Megawizard because in the example project, the node name is known and then the <variation name>_example_if0_p0.sdc file will create “local_pll_driver_core_clk”.


The workround for this issue:
1. Create a new sdc file such as sdc1.sdc and create the clock constraint for the clock used for the driver and MPFE ports. Set the clock name as “user_driver_clock”.
2. Add sdc1.sdc into project and place it in the order before <variation name>_p0.qip in QSF.
3. Change the following line in the <variation name>_p0.sdc file
Change From
set_min_delay -from -to 0.500
set_min_delay -from [get_clocks { user_driver_clock }] -to 0.500