You will see this critical warning message if you compile DDR3 Controller with UniPHY with the following assignment. In this case, the Quartus® II software cannot find
set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES OFF
The Quartus II software will look for
*:s0|*:sequencer_scc_mgr_inst|scc_state_curr.STATE_SCC_IDLE to search
pll_config_clock. The state will disappear if you disallow state machine generation thus the Quartus II software cannot find the clock.