Device Family: Intel® Arria® 10 GT

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Device Family: Arria® V GZ

Device Family: Arria® V ST

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Device Family: Cyclone® V GT

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Device Family: Stratix® V GT

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Type: Answers

Area: Intellectual Property


IP Product: PCI Express 1/2/4/8 Lanes (x8)

Why does the Avalon-MM DMA Hard IP for PCI Express design stop receiving data?

Description

If the RdDmaWaitRequest_i signal is asserted for an extended period of time, the internal storage of the Read DMA Module becomes full, causing the Hard IP for PCI Express® receive FIFO to become full.  Once the FIFO is full, processing of incoming packets stops for as long as the RdDmaWaitrequest_i signal is asserted.

Workaround/Fix

Redesign your RTL to avoid issuing RdDmaWaitRequest_i.  Alternatively, limit its duration to a few clock cycles per transaction.