Device Family: Intel® Arria® 10 GT, Intel® Arria® 10 GX, Intel® Arria® 10 SX, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: Component



Why might the Altera Power Distribution Network (PDN) Tool, Auto Decoupling Mode result in a Zeff that is too high?

Description

Using the Altera® Power Distribution Network (PDN) Tool, Auto Decoupling Mode may result in a Zeff that is too high This might happen if the user-entered PCB parameters result in an inefficient PDN, and the current to be decoupled by that PCB is unrealistically high.

With difficult PCB and current parameters, the Auto Decoupling Mode will continue to add decoupling capacitors until it determines they are having negligible effect, resulting in hundreds of capacitors. Decoupling schemes with similar performance can be achieved manually with far fewer capacitors.

Workaround/Fix

As well as decoupling manually, you can reduce the decoupling burden by accurately estimating your current requirements and making your PCB more efficient.

You might be able to reduce your PCB current requirements in the following ways:

  • Estimating realistic current requirements in the Altera Early Power Estimator (EPE).
  • Entering realistic "Toggle Rate" figures for the logic in the EPE. Unrealistic high toggle rates dramatically increases dynamic current requirements.
  • Entering realistic logic requirements in the EPE.
  • Entering realistic clock frequencies in the EPE.
  • Using the Quartus® II software (Power Play Power Analyser) PPPA and .vcd simulation entry for accurate current requirement estimation.
  • Considering Root Sum Squared (RSS) averaging for shared power supply rails. You can refer to the "Introduction" tab of the PDN Tool for more information on this method.

The PCB can be made more efficient in the following ways:

  • Increasing inter-plane capacitance of your Power (PWR) and Ground (GND) plane pair by reducing their dielectric thickness.
  • Increasing inter-plane capacitance of your PWR and GND plane pair by increasing their surface area.
  • Reducing loop inductance from the PWR and GND plane pair to the FPGA by moving them closer to the surface of the PCB that the FPGA is mounted to.
  • Reducing loop inductance from the high frequency decoupling capacitors to the PWR and GND plane pair by placing them on the surface of the PCB that is closest to the planes.
  • Using Via On Side (VOS) instead of Via On End (VOE) capacitor mounting topologies to help at high frequencies.
  • Using ultra-low (Effective Series Inductance) ESL mounting capacitors to help at high frequencies. For instance X2Y package style.
  • Using ultra-low (Effective Series Resistance) ESR bulk capacitors to help at low frequencies,
  • Considering larger vias with less ESL.

Realistic tool entry can make decoupling easier to achieve. The following factors affect the calculation of Ztarget:

  • An increase in dynamic current reduces Ztarget and makes decoupling difficult to achieve. See the guidelines above.
  • Enter realistic noise" or ripple figures into the PDN tool. The noise figure should be taken from the device and rail specific table in the "Introduction" tab of the PDN Tool. You should not use the DC specification from the device datasheet. Unrealistic ripple requirements reduce Ztarget and make decoupling difficult.
  • Enter realistic transient % figures into the PDN tool. The tansient % figure should be taken from the device and rail specific table in the "Introduction" tab of the PDN Tool. Unrealistic transient % requirements reduce Ztarget and make decoupling difficult.