Yes, there are channel placement restrictions when implementing bonded transceiver channels using the Quartus® II software for Stratix® V GX, GS, and GT devices.
Logical lane 0 must be assigned to a channel that is equipped with a central clock divider. In Stratix V transceiver devices, this is channel 1 or 4 within the transceiver bank which is shown in bold for the examples below.
If using an ATX PLL as the Tx PLL, logical lane 0 must be placed on:
- Channel 1 or channel 4.
- This requirement limits the number of possible bonded interfaces per transceiver bank to two.
GXB_[Tx,Rx]_[L,R][5,11,17,23] = Logical lane 5
GXB_[Tx,Rx]_[L,R][4,10,16,22] = Logical lane 4
GXB_[Tx,Rx]_[L,R][3,9,15,21] = Logical lane 3
GXB_[Tx,Rx]_[L,R][2,8,14,20] = Logical lane 2
GXB_[Tx,Rx]_[L,R][1,7,13,19] = Logical lane 0
GXB_[Tx,Rx]_[L,R][0,6,12,18] = Logical lane 1
If using a CMU PLL as the Tx PLL, logical channel 0 must be placed on:
- Transceiver channel 1 if channel 4 is used as a CMU
- Transceiver channel 4 if channel 1 is used as a CMU
- This requirement limits the number of possible bonded interfaces per transceiver bank to one.
GXB_[Tx,Rx]_[L,R][5,11,17,23] = Logical lane 1
GXB_[Tx,Rx]_[L,R][4,10,16,22] = Logical lane 0
GXB_[Tx,Rx]_[L,R][3,9,15,21] = Logical lane 2
GXB_[Tx,Rx]_[L,R][2,8,14,20] = Logical lane 3
GXB_[Tx,Rx]_[L,R][1,7,13,19] = Used as a CMU
GXB_[Tx,Rx]_[L,R][0,6,12,18] = Unused
Failing to follow the logical channel 0 placement requirement will result in a Quartus II software error similar to the one shown below.
Error: Illegal constraint of Transmitter channel for I/O tx_serial_data[0] to the region (210, 21) to (210, 21): no valid locations in region
Info: Atom I/O pad tx_serial_data[0] is constrained to the location PIN_AK4 due to: User Location Constraints (PIN_AK4)
Error: Could not find location for Transmitter channel for I/O tx_serial_data[0] that enable routing of bonding clock lines
This restriction is scheduled to be removed in a future version of the Quartus II Software.
To work around this restriction you can set the Bonding Mode to PLL Feedback Compensation (fb_compensation) in the transceiver Megawizard™.
You must still adhere to the contiguous channel placement requirement.