Device Family: Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Cyclone® V E, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX, Stratix® III, Stratix® IV E, Stratix® IV GT, Stratix® IV GX, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property

IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Why do I see bit errors with my DDR3 controller?


You may see bit errors with your DDR3 UniPHY memory controller if the REFRESH command period, tRFC, is set too low. The memory controller could perform READ or WRITE commands before the REFRESH cycle has completed causing the corruption of data. Make sure to set the tRFC timing parameter in the Megawizard GUI to the correct value specified in the memory device datasheet.