Device Family: Stratix® III

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller supporting ALTMEMPHY

Why must I connect PLL input to a dedicated clock input pin for ALTMEMPHY based memory controller design?

Description

In order to minimize output clock jitter, reference input clock pin to the ALTMEMPHY PLL must not be routed through the core using global or regional clock networks.

 

The reference input clock signal to the PLL must be driven by the dedicated clock input pin located adjacent to the PLL, or from the clock output signal from the adjacent PLL.

 

Input and output delays are only fully compensated for when the dedicated clock input pins associated with that specific PLL are used as the clock source.

 

If the clock source for the PLL is not a dedicated clock pin for that specific PLL, jitter is increased, timing margin suffers, and the design may require an additional global or regional clock.

 

Hence, dedicated PLL input clock pin is strongly commended for clock source for ALTMEMPHY PLL.

 

If the reference clock is cascaded from another PLL, that upstream PLL must be configured in No compensation mode and Low bandwidth mode.