In some cases you may need to reset the Configuration Space and datapath portions of the Altera® Hard IP for PCI Express® IP core, without resetting the PLLs or SERDES components. The pin_perst and npor signals reset the Hard IP, the PLLs, and the SERDES components.
Device Family: Intel® Arria® 10 GX
Device Family: Intel® Arria® 10 SX
Device Family: Arria® V GT
Device Family: Arria® V GX
Device Family: Arria® V GZ
Device Family: Arria® V ST
Device Family: Arria® V SX
Device Family: Stratix® V GS
Device Family: Stratix® V GT
Device Family: Stratix® V GX
Area: Intellectual Property
Refer to the Reset Controller Block Diagram figures in the Cyclone® V, Stratix® V, or Arria® V Hard IP user guides or the Reset Controller in Arria 10 Devices figure in the Arria 10 Hard IP user guides.
The reset controller drives the srst (state machine reset) and crst (Configuration Space reset) signals inside the altpcie_<dev>_hip_256_pipen1b.v module. You must OR your user-defined reset signal with these signals. You must repeat this manual change every time you regenerate your IP core.
The user-defined reset must be level sensitive and synchronous to pld_clk.
srst and crst must assert and deassert together. You must OR both signals with the user-defined reset.